133 questions
0
votes
0
answers
31
views
Can I insert a folder (directory) instead of a file as a BlackBox in Chipyard?
I am trying to configure an MMIO Peripheral (= MMIO Accelerator, 11page) consisting of a 4x4 NoC in Chipyard. In this process, I would like to insert a SystemVerilog-based NoC as a BlackBox. However, ...
2
votes
0
answers
67
views
RISC-V bare-metal simulation problem, increasing .rodata array size causes hang during DMA
I am trying to write data starting at a specific address (0x88000000) of the memory (simulated DRAM size is 256 MiB), once all data is written, the DMA unit is programmed using the MMIO registers. The ...
- 182
0
votes
0
answers
45
views
Problem with Tilelink protocol handshake between Rocket Core and a MMIO device
I am trying to add a MMIO device to rocket-chip in chipyard and I want to use Tilelink interface. This MMIO device is intended to be a slave and the rocket-core as the master. For this, I created a ...
- 182
0
votes
1
answer
94
views
Running test on Rocket core CPU - global variable initialized to 0 is unsuccessful, output wrong value instead
While I am benchmarking my Rocketcore CPU, I encountered failed Coremark benchmarking. After some debug, I reduce the issue scope to unsuccessful global initialization of 0 value. In Coremark, it will ...
- 119
0
votes
1
answer
125
views
Rocket-Chip generator environment setup
I tried to set up the rocket-chip generator environment. I cloned the git repository and updated the submodules as follows:
$ git clone https://github.com/ucb-bar/rocket-chip.git
$ cd rocket-chip
$ ...
1
vote
0
answers
116
views
How to obtain emulator binary in latest rocket-chip using mill and chisel 5.0.0?
I've setup Chisel 5.0.0 and firtool as I explained in this other question. I also installed successfully mill and rocket-tools as instructed here and here.
This prepared the stage for getting the ...
- 319
1
vote
1
answer
178
views
Try to compile and install rocket-chip generator but scala reports a constant pool index error
Here is the bug report:
macros.compile scala.reflect.internal.FatalError:
bad constant pool index: 0 at pos: 48461
while compiling: <no file>
during phase: globalPhase=<no ...
- 31
0
votes
1
answer
207
views
Issue with Threads in embedded system
I have 4 Rocket RISC-V cores and each are connected to 4 identical accelerators. What I am trying to do is to use multithreading to run all or some of the accelerators at the same time and compare the ...
- 182
2
votes
1
answer
630
views
Generating verilog file for rocket chip
I am a beginner working with rocket chip generator for my project but I am not able to generate the verilog file for it and facing this error. I am using an apple M1 chip macOS. I started with cloning ...
0
votes
1
answer
221
views
Build rocket-tools for gcc-13
I'm following the instructions in rocket-chip v1.6 to install and run rocket-chip. As mentioned there, I need to install rocket-tools first (it's not mentioned what version of rocket-tools is ...
0
votes
1
answer
523
views
Rocketchip: make failing under /emulator and /vcs due to "mill: command not found"
Discussed in https://github.com/chipsalliance/rocket-chip/discussions/3492
Originally posted by AnuragMalwee September 20, 2023
Hi, I am building the rocket-chip project for the first time, and never ...
0
votes
1
answer
162
views
sbt test does not work and all the tests fail
I have installed rocket-chip and it needs chisel to compile i have also downloaded chisel , but when i run sbt test all the tests fail, am i doing something wrong . is there an alternative for sbt ...
- 3
0
votes
1
answer
104
views
How to export TileLink node to LazyModule's output and generate respective verilog file
I am trying to create a simple module with tilelink client connected to modules output. How to do it? Have been trying to figure it out for 20 hours at this, I am completly lost.
I am trying the ...
- 1
0
votes
1
answer
52
views
Rocket chip didn't work when using large array
I am simulating baremetal executables on Rocket chip with verilator. When I use a large array like
float a[3][224][224]
the simulation in verilator will not work successfully.
Here is my main.cpp:
int ...
0
votes
1
answer
39
views
Separate reset domain for RocketTile?
Is there a way to wire RocketTile to a separate (external) reset signal, so that the tile can be held in reset while the rest of the system is active?
The code seems to support a separate reset domain ...
- 324