1,431 questions
2
votes
1
answer
39
views
Risc-v compressed instruction alignment
When supported, compressed instructions (RVC) bring a relaxation of code address alignment from 4 to 2 bytes.
They also bring the possibility to intermix compressed and non-compressed instructions.
...
- 3,493
-2
votes
0
answers
33
views
how to translate (riscv) 'jr _start' to opcode
I have a question: How do I translate (RISC-V) 'jr _start' to an opcode?
I need this for jumping to the kernel in U-Boot.
Thank you
- 1
-1
votes
0
answers
85
views
Synthesis and Implementation Problems Caused by the Simultaneous Use of posedge and negedge in an always Block
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I am working on a basic processor design exercise for RISC-V.
My goal is to improve branch performance by moving the branch decision from the EXE (Execute) stage to the ...
0
votes
0
answers
83
views
How does a failed spinlock CAS affect out-of-order speculation and RMW reordering on weak memory architectures?
I’m trying to understand how speculative execution interacts with weak memory models (ARM/Power) in the context of a spinlock implemented with a plain CAS. Example:
// Spinlock acquisition attempt
if (...
- 1,385
1
vote
0
answers
57
views
RISC-V a1 register assumptions after ecall execution
As explained here it's clear to me that user-space calling conventions don't apply when dealing with kernel-space system call execution, so basically no register is clobbered after an ecall ...
2
votes
0
answers
67
views
RISC-V bare-metal simulation problem, increasing .rodata array size causes hang during DMA
I am trying to write data starting at a specific address (0x88000000) of the memory (simulated DRAM size is 256 MiB), once all data is written, the DMA unit is programmed using the MMIO registers. The ...
- 182
-1
votes
0
answers
64
views
Risc-V read after write hazard pipeline forwarding
I'm working on a pipelined risc-v processor from the Computer Organization and Design RISC-V edition book.
The book states:
We assume that the write is in the first half of the clock cycle and
the ...
- 9
-1
votes
1
answer
101
views
LLVM generates stack usage on simple RISC-V function where GCC doesn't
I have a simple function:
extern "C" Variant test_bool(bool arg) {
return arg;
}
Built with mostly standard settings (I removed part of the paths):
zig c++ -target riscv64-linux-musl -I/...
- 547
0
votes
1
answer
55
views
RISC-V GCC Force Linker Relaxation with GP Register to Address Static Data
I'm writing a bare-metal firmware for a virtual RISC-V SoC. Below is code that communicates with a physical device on the SoC and it is using constant data from the my_data array that sits in ROM. The ...
- 81
0
votes
0
answers
88
views
RISC-V vs C Code Comparison for Simple Multiply and Accumulate (MAC) Operation
We tried profiling a simple MAC operation using both RISC-V Vector (RVV) intrinsics and plain C code. Surprisingly, the C version performs better, even though the intrinsics code processes 16 ...
- 1
1
vote
0
answers
140
views
Function Call leads to infinite loop
I've been trying to get a program running on the QEMU emulator. The issue is that when I pass an empty string or a non-empty string to the print function, the program prints ABC indefinitely.
#[unsafe(...
0
votes
0
answers
48
views
RISC-V Spike: "Illegal Instruction" for Custom R-Type matmul - Match/Mask Not in Generated Dispatcher
I'm adding a custom R-type instruction matmul rd, rs1, rs2 to RISC-V Spike. Despite my efforts, I'm getting an "illegal instruction" error.
Toolchain & Assembly:
Modified riscv-binutils-...
4
votes
1
answer
75
views
GNU as recursive/loop macro expected output
In this assembly file below, the macro jump_table should automagically create ... a jump table to consecutively numbered labels like jump_0, jump_1, ... jump_<n>.
It seems there is no loop ...
- 3,493
2
votes
1
answer
97
views
Context switch in interrupt routine
I am writing an interrupt routine for RISC-V. Interrupts occur in U-mode and are handled in S-mode.
Upon an interrupt, I want to save the user execution context on the kernel stack of the thread that ...
- 173
1
vote
1
answer
89
views
Why __sync_or_and_fetch builtin in a loop renders as an endless loop with -O2 and -O3?
[SOLVED] Use __sync_fetch_and_or instead of __sync_or_and_fetch! The double amoor instruction maybe is still a bug.
[Disclaimer] This could be a bug in GCC but I am still new to RISC-V assembly to be ...
- 3,493